Delta-sigma modulators are particularly useful in digital-to-analog and analog-to-digital converters (DACs and ADCs). Using oversampling, a delta-sigma modulator spreads the quantization noise power across an oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, the delta-sigma modulator performs noise shaping by acting as a low-pass filter to the input signal and a high-pass filter to the noise; hence, most of the quantization noise power is thereby shifted out of the signal band.
The typical delta-sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, quantizer and a feedback loop with a digital-to-analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in a higher order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. Higher-order modulators have improved quantization noise transfer characteristics over those of lower order, but stability becomes a more critical design factor as the order increases.
Switched-capacitor filters/integrators are useful in a number of applications including the integrator stages in delta-sigma modulators. Generally, a basic differential switched-capacitor integrator samples the input signal, and often a reference voltage as well, onto a corresponding pair of sampling capacitors during the sampling (charging) phase, in a process sometimes referred to as “double sampling.” During the following second phase, the charge on the sampling capacitor is transferred at the summing nodes of an operational amplifier to a corresponding pair of integrator capacitors in the amplifier feedback loops. The operational amplifier drives the integrator output. An example input network 100 for a delta-sigma modulator is depicted in FIG. 1.
Example input network 100 of FIG. 1 generally operates in accordance with a clock signal CLK, the complement of which is a signal CLK′. Each of clock signals CLK and CLK′ may comprise a square-wave signal, as shown in FIG. 1. Clock signals CLK and CLK′ may define clock cycles operating at a sampling rate wherein each clock cycle includes a first phase when clock signal CLK is high and clock signal CLK′ is low and a second phase when clock signal CLK is low and clock signal CLK′ is high. Generally, during the first phase of each cycle, switches 102 and 108 close and charges proportional to the voltages v+ and v− at the inputs to input network 100 are respectively sampled onto cross-coupled sampling capacitors 110a and 110b, respectively. During the second phase of each cycle, switches 104 and 106 close, and the input voltages v+ and v− are coupled to the input plates of sampling capacitors 110a and 110b, respectively. Consequently the charges sampled onto sampling capacitors 110a and 110b during the first phase are respectively forced onto integration capacitors 114a and 114b which are each coupled between inputs and outputs of an integrator 112.
Differential double sampling is often advantageous as it increases signal-to-noise ratios as compared to single-ended sampling because the effective signal input is doubled. In addition, differential double sampling effectively doubles the sampling rate, relaxing requirements for anti-aliasing filtering of the input network 100. However, differential double sampling effectively reduces the input impedance present at the input of input network 100 as compared to single-ended sampling. The low input-impedance results in an increase in total harmonic distortion (THD) due to an anti-aliasing filter present at the input of input network 100 (not explicitly shown in FIG. 1). The signal-dependent charge injected in the network 100 ultimately returns to the anti-alias filter, and because input-impedance of the network 100 is lower than that of its single sampling counterpart, it creates larger voltage over a resistor of the anti-alias filter, resulting in the signal distortion. Therefore, the low input impedance may undesirably load the anti-aliasing filter, cause loss, and also cause undesired harmonic distortion in the input differential signal.
Accordingly, to reduce such disadvantages, it may be desirable to increase effective impedance of the input network of a delta-sigma modulator when double sampling is employed. A number of solutions to provide for such increased impedance have been proposed, but such solutions have shortcomings and disadvantages.
For example, in one solution, a buffer is used which, during a portion at the beginning of the sampling phase, each polarity of the differential input signal is used to pre-charge sampling capacitors (e.g., capacitors 110a and 110b) of the input network, after which the sampling phase continues and inputs are sampled similarly to that described above. However, such an approach requires high-bandwidth and power-hungry buffers if active buffers are used, and a high-bandwidth analog front end if passive buffers are used. In addition, input impedance increases based on a gain of the buffers, thus increasing risk of signal distortion.
In another solution, during a portion of the beginning of the sampling phase, sampling capacitors (e.g., capacitors 110a and 110b) are discharged to a common-mode voltage equal to (v++v+)/2. However, such an approach only leads to a doubling of the effective input impedance.
Hence, for applications requiring delta-sigma modulation, improved techniques for increasing of the input impedance at the input sampling network, are desired.